Problems with state of the art static random access memory (SRAM) write assist techniques include consumption of too much area and power, which increase die, packaging, cooling and operating costs, and limited performance improvement due to functional limitations, such as setup time requirements and interfaces between SRAM and peripheral control circuitry that limit SRAM performance (e.g., operating speed). Accordingly, there is a need to overcome one or more drawbacks and deficiencies in the state of the art.